1. Field of the Invention
The present invention relates to a synchronous binary counter as well as to a frequency synthesizer which is obtained from the binary counter by causing said synthesizer to divide its own clock frequency and by employing only the last output of the counter.
The counter in accordance with the invention can be employed in a number of different ways in the form of discrete components or integrated circuits by making use of bipolar transistors or field-effect transistors but is of interest primarily in the microwave frequency field in the form of an integrated circuit on high-speed materials such as GaAs or other group III-V materials.
2. Description of the Prior Art
There are a number of means in existence for constructing binary counters, the most simple expedient being to mount scale-of-two dividers in cascade. In the case of high-ratio divisions, however, the last stages must be very stable by reason of the periods of increasing length. In point of fact, the static flip-flops employed in the prior art are not always sufficiently stable.
The synchronous binary counter in accordance with the invention can be constructed with static flip-flops but also with dynamic flip-flops which are faster, have lower power consumption and call for a smaller number of components, which is an advantage in the field of integrated circuit fabrication. However, the primary advantage of the counter circuit in accordance with the invention is that it operates with a single high-frequency clock signal and therefore has much higher stability. In more precise terms, the two clock signal which actuate the counter are the two complementary signals of a single clock. There is therefore no relative displacement between them since they are derived from a single clock signal.